Designed and developed a System-on-Chip (SoC) daughter board for the Caravel eFabless SoC platform. The project involved creating a compact 2-layer M.2 form factor board that integrates all necessary components for SoC bring-up and development.
The board design included power regulation circuits to provide stable voltage rails for the SoC, clock generation circuitry, memory interfaces, and USB-UART communication for debugging and programming. The design required careful attention to signal integrity, power distribution, and thermal management.
I wrote SystemVerilog modules for RISC-V SoC functionality, implementing various IP blocks and validating their operation. The validation process involved extensive testing using ERC (Electrical Rule Check) analysis, signal direction analysis, and hardware bring-up testing.
The project validated multiple communication protocols including SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver-Transmitter), and I²S (Inter-IC Sound) interfaces, ensuring proper functionality of the SoC and its peripherals.
This project was completed as part of the SoCET (System-on-Chip Engineering Team) at Purdue University. The goal was to design and validate a daughter board for the Caravel eFabless SoC platform.