Project
Caravel eFabless SoC Daughter Board
Designed an M.2 daughter-board schematic for Caravel eFabless chiplet integration, combining power regulation, clock generation, flash memory, and USB-UART interfaces.
Technologies
Overview
Designed and developed a daughter-board schematic for integrating the Caravel eFabless chiplet within Purdue's SoCET (System-on-Chip Engineering Team). The modular M.2 interface combines power delivery and communication in a compact, standardized form factor.
I owned the M.2 connector interface and collaborated with Seokjae Kim on the remaining system integration. The design incorporated TLV761 voltage regulators for 1.8 V and 3.3 V rails, a 10 MHz DSC6001 MEMS oscillator, W25Q32JV flash memory, and an FT232H USB-to-UART bridge with TXS0101 level shifting for the Caravel 1.8 V UART lines.
We reviewed component datasheets, divided subsystem ownership, and refined the integrated schematic through design reviews with project leads. Electrical Rule Check issues involving power flags and floating inputs were resolved, and pin direction, voltage-domain separation, and signal connectivity were verified.
The final schematic completed interface-level matching for Caravel's SPI, UART, and I²S subsystems. The project concluded before PCB layout and fabrication, leaving a reviewed schematic ready to support future layout, prototyping, and hardware testing.
Project Context
Completed as part of Purdue University's VIP SoCET team, this project focused on a modular daughter-board schematic for Caravel eFabless chiplet integration. I was responsible for the M.2 connector interface and shared responsibility for integrating the remaining subsystems.
Key Features
- Standardized M.2 connector interface for communication and power delivery
- TLV761 regulation for 1.8 V and 3.3 V power domains
- 10 MHz DSC6001 MEMS clock source
- W25Q32JV flash-memory integration
- FT232H USB-to-UART bridge with TXS0101 level shifting
- Interface-level matching for SPI, UART, and I²S subsystems
Challenges
- Integrating independently owned subsystems into one coherent schematic
- Separating and translating 1.8 V and 3.3 V signal domains
- Resolving ERC power-flag and floating-input issues
- Verifying pin direction and signal connectivity across Caravel interfaces
Results
- Integrated all planned components into the final schematic
- Passed Electrical Rule Check after resolving power and input issues
- Verified voltage-domain separation, pin direction, and signal connectivity
- Produced a reviewed foundation for future PCB layout and testing